A portion of the buffer cycle in which the logic or arithmetic unit must cease operation or neither will be able to communicate with the memory unit.

缓冲存储器周期的一部分，在这期间，逻辑与算术运算器必须中止操作或不能与存储器传输信息。

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The improved model of input buffer presented is to insert a quasi random memory between input queue and arbitration logic at ATM switching unit.

改进的输入缓冲方案是在AT M交换单元的输入队列和仲裁逻辑之间加入一个准随机存储器。

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The crucial path includes address buffer, decoder, memory unit, sense amplifier and output buffer.

其中包括地址缓冲、译码器、存储单元、灵敏放大器和输出缓冲电路。

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