This paper introduces the theory of the phase-locked loop (PLL) and the direct digital synthesis (DDS), a method to improve the precision of DDS and reduce its phase truncation error is also given.

介绍了锁相环(PLL)技术和直接数字式频率合成(DDS)技术的基本工作原理，给出了一种提高DDS输出频率精度及减小其相位截断误差的方法。

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Then presented the basic structure, phase model, frequency response and performance analysis for noise and spur, of phase locked loop (PLL).

然后介绍了锁相环(PLL)的基本结构、相位模型、频率响应、噪声及杂散性能。

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The design and implementation of quadrature waveform generator are described based on the AT89C52, phase-locked loop(PLL) and switched-capacitor filter(SCF).

描述了基于AT89C52单片机、锁相环和开关电容滤波器的正交信号发生器的设计和实现方法。

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