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slave clock

  • [天] 子钟

网络释义专业释义英英释义

  从时钟

从时钟

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短语

slave clock adjust 副钟调整

digital slave clock 数字子钟

slave clock generator 从动的时钟发生器

  • 从时钟 - 引用次数:1

    参考来源 - 精确时钟同步协议最佳主时钟算法 Best master clock algorithm of precision clock synchronization protocol
  • 子钟
  • 子钟
    副钟

·2,447,543篇论文数据,部分数据来源于NoteExpress

Slave clock

  • abstract: In telecommunication, a slave clock is a clock that is coordinated with a master clock. Slave clock coordination is usually achieved by phase-locking the slave clock signal to a signal received from the master clock.

以上来源于: WordNet

双语例句

  • With the signal from the master clock, the slave clock is able to recover an accurate local clock signal using a Clock Recovery Phase Locked Loop (PLL).

    时钟利用时钟发来的时钟信号通过数字锁相环恢复本地时钟信号。

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  • It is shown by theory and case study that the master - slave clock mode in a com munication system is ideal for proper functions of the current differential protection.

    理论实例分析表明,通信系统—从时钟方式电流差动保护装置复用数字通信系统时正确工作理想方式。

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  • The micro-processor and VLSIC are core of the master clock, which consists of a control unit and can adjust all slave clocks (except standard time slave clock) clockwise and inversion quickly.

    器件核心构成控制单元,操作非常简单,且可以同时所有钟进行顺时针逆时针快速调整,运行可靠。

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