sub micron CMOS 深亚微米CMOS
Sub-micron CMOS IC 亚微米CMOS
deep sub-micron cmos 深亚微米cmos
very deep sub-micron cmos technology 深亚微米cmos工艺
A static verification methodology for circuit design-flow of ASIC's based on very deep sub-micron CMOS technology is described in the paper.
介绍了基于深亚微米cmos工艺asic电路设计流程中的静态验证方法。
It has been demonstrated that compared to simulator-based method, manufacturable deep sub-micron CMOS analog circuits can be synthesized using this system in a short run time.
大量的实验结果表明：与基于模拟器的方法相比，采用该系统可以快速综合出可制造的深亚微米cmos模拟单元电路。
In this paper, design technologies of sub-micron CMOS gate array, such as building library, testability, clock design, power-ground design, architecture optimizing, margin design, are presented.
本文主要论述亚微米cmos门阵列的设计技术，包括建库技术，可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等，最后给出了应用实例。
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