Static timing analysis is widely applied in timing verification because of its high speed and great capacity. The gate delay computing is a critical part of static timing analysis.
静态时序分析由于速度快和容量大而广泛应用于时序验证，而门延时的计算则是静态时序分析中的关键部分。
Firstly, false paths in static timing analysis and the algorithm to sensitize paths are presented, and then some factors affecting gates and interconnects delay are discussed.
首先，文章讨论了静态时序分析中的伪路径问题以及路径敏化算法，分析了影响逻辑门和互连线延时的因素。
We accomplished the full-chip static timing analysis of X microprocessor, and made a detailed analysis such as critical-path checking in the circuit.
参与并完成了X微处理器全芯片的静态时序分析工作，对电路的关键路径等重要信息进行了详细分析。
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