This paper presents a high speed test generation method specifically for upper large scale combination circuit (ULSCC) and full scan designed circuit.
针对特大规模组合电路和全扫描设计电路提出了一种高速测试生成方法。
In the upper left corner of the figure, large-scale and institution-based or supported initiatives are found.
在图中的左上角可以发现大规模的和基于机构的或受支持的举措。
In the upper right corner of Figure 1, large-scale, non-institution-based operations are placed.
不基于机构的大规模运作位于图1中的右上角。
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