In this thesis we discuss such a DSP, which USES a clustered VLIW architecture and can perform multiple operations simultaneously during a single clock cycle.
本文讨论这样一款DSP，它采用分簇的VLIW体系结构，能够在单个时钟周期同时执行多个操作。
Devadas has demonstrated that small circuits connected to the cores can calculate the allotment of bandwidth and switch the direction of the connections in a single clock cycle.
Devadas已经成功演示了一种能计算带宽分配且能在一个时钟周期内改变连接传输方向的小型电路。
This is the number of operations that must be completed in a single cycle of clock time.
这是在一个时钟周期内必须完成的操作数量。
Another unique architectural feature is the memory system which allows an instruction fetch and at the same time a data access by each individual core at every single clock cycle.
另一个独特的构架特性是内存系统，它允许一个取指，并在同一时间，每一个核可以读取数据在每一个单独的时钟周期内。
Another unique architectural feature is the memory system which allows an instruction fetch and at the same time a data access by each individual core at every single clock cycle.
另一个独特的构架特性是内存系统，它允许一个取指，并在同一时间，每一个核可以读取数据在每一个单独的时钟周期内。
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