Optimization in automatic logic synthesis is usually done after the Boolean equations are set up.
逻辑自动综合中控制部分的优化一般是在布尔方程确定之后进行。
Recent years, being one of the most difficult problems, automatic logic synthesis for large scale PLDs has gained more and more attention.
大规模集成PLD器件的逻辑综合是近年来引起广泛关注的热点和难点问题。
The above work is intended to set up an automatic logic synthesis system to translate a register transfer level language descriptions into hardware logic diagrams.
上述工作是为了建立一个将寄存器传输级语言描述翻译成硬件逻辑图的自动逻辑综合系统。
The above work is intended to set up an automatic logic synthesis system to translate a register transfer level language descriptions into hardware logic diagrams.
上述工作是为了建立一个将寄存器传输级语言描述翻译成硬件逻辑图的自动逻辑综合系统。
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