The error messages you will get from clock skew will not generally be obvious.
在时钟问题中产生的错误消息通常都不太明显。
Fix: the Kerberos authentication protocol requires that the clock skew between a server and a client is no greater than 5 minutes.
解决方案：Kerberos身份验证协议要求服务器和客户机之间的时钟差不大于5分钟。
Clock signal and clock skew become more and more important in the circuit performance.
时钟信号和时钟偏差对电路性能的影响也越来越明显。
A yield driven clock skew scheduling algorithm is proposed in presence of process variations.
针对工艺参数变化的情况，提出一种成品率驱动的时钟偏差安排算法。
In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.
为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓冲器。
In clock routing, clock signal and clock skew become more and more important for impact of the circuit performance.
在时钟布线中，时钟信号和时钟偏差对电路性能的影响越来越明显。
Knowledge of process variation is important to optimize critical path delay, minimize clock skew, and reduce crosstalk noise.
过程变化的知识对于最优化电路延时，减少时钟倾斜和降低串扰噪声很重要。
Serial communications based on SERDES adopt the clock_data recovery(CDR) instead of both data and clock transmitting, which solve the problem of clock skew.
基于SERDES的串行通信过程中采用时钟和数据恢复技术（CDR）代替同时传输数据和时钟，从而解决了限制数据传输速率的信号时钟偏移问题。
The design of asynchronous circuits is widely used in modern VLSI design, which is able to resolve the problems of power dissipation, system speed, clock skew, etc.
异步电路的设计能够解决功耗、系统速度、时钟偏移等问题，成为当前VLSI研究的热点。
A new clock skew scheduling algorithm is proposed. This algorithm generates timing constraints which can effectively promote the area optimization of logic syn thesis.
提出了一种新的时钟偏斜规划算法，该算法所生成的时序约束可以有效地促进逻辑综合工具的面积优化。
Concerning the clock skew and clock drift problem in wireless sensor networks, some different methods of synchronization time on synchronization accuracy were studied.
针对无线传感器网络固有的时钟偏移和时钟漂移问题，研究了不同的时间同步方法对同步精度的影响。
Phase matching is of particular concern with some high speed digital circuits, because unmatched cables may cause excessive clock skew, resulting in erroneous operation.
由于不匹配的电缆可引起过度的时钟相偏（Clock Skew），导致错误操作，所以相位匹配是有些高速数字电路中特别要注意的事项。
Clock Tree Synthesis is important in the backend-end design of chip design, and the clock skew has become the major part of constraints that limit system clock frequency.
时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。
To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can dynamically adjust and reduce the clock skew after a chip is manufactured.
为了克服制程、电压、温度变异所造成的影响，自动时脉偏移同步方案可以在晶片制造出来之后动态地调整并降低时脉偏移。
Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.
此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓冲器。
Experiment results show that this approach can efficiently reduce area of logic synthesis results compared with the traditional clock skew scheduling algorithm, without degrading the performance.
实验结果表明：按权重分配裕量的方法相对于平均分配裕量，能够在不降低电路性能的情况下，更加有效地降低逻辑综合结果的面积。
Experiment results show that this approach can efficiently reduce area of logic synthesis results compared with the traditional clock skew scheduling algorithm, without degrading the performance.
实验结果表明：按权重分配裕量的方法相对于平均分配裕量，能够在不降低电路性能的情况下，更加有效地降低逻辑综合结果的面积。
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