Decision diagram model is a utility to represent data dependence between signals in VLSI designs, and is widely used in VLSI design verification.
决策图模型描述了VLSI设计信号间的数据依赖关系，在VLSI设计验证中有广泛的应用。
Decision diagram model is a utility to represent data dependence between signals in VLSI designs, and is widely used in VLSI design verification.
决策图模型描述了VLSI设计信号间的数据依赖关系，在VLSI设计验证中有广泛的应用。
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