The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic.
这款双通道adc内核采用多级、差分流水线架构，并集成了输出纠错逻辑。
The principle of modulation, demodulation and data error correction based on multi-valued logic is given in the text. And the expression of data error correction is deduced.
文中给出了多值逻辑条件下数据的调制解调原理和纠错原理，并推导出数字就错的最终求解公式。
We propose a novel architecture with error detection and error correction abilities called complementary logic - alternating-complementary logic (CL-ACL) structure.
提出了具有差错检测和校正能力的、延迟较小的互补-交替互补逻辑结构。
We propose a novel architecture with error detection and error correction abilities called complementary logic - alternating-complementary logic (CL-ACL) structure.
提出了具有差错检测和校正能力的、延迟较小的互补-交替互补逻辑结构。
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