A modulator reduces the quantization error of the frequency divider.
调制器减少该分频器的量化误差。
This paper describes a noise analysis method for a phase switching frequency divider.
介绍了一种相位开关型分频器电路的噪声分析方法。
A high frequency low power divide-by-2 Injection-Locked Frequency Divider is presented.
设计了一个高频低功耗的注入锁定二分频器。
Experiment of fourfold frequency divider proved the feasibility and validity of the method.
四倍分频器电路演化实验结果验证了该方法的可行性与有效性。
A frequency low power divide - by - 2 Injection - Locked frequency Divider (ILFD) is presented.
设计了一个高频低功耗的注入锁定二分频器。
The logic and circuit design of a very high speed ECL programmable frequency divider is described.
介绍一种ECL高速程控分频器的逻辑设计、电路设计及研制结果。
Finally, a brief introduction to the applications of the very high speed frequency divider is given.
最后简单介绍了超高速分频器的应用情况。
The mean frequency synthesizer which usesfrequency divider given here is successfully used in the B …
文中给出的分频法平均频率合成器已成功地用于作者所设计的B超仪中。
This paper gives out a design of the equal duty ratio arbitrary integer frequency divider based on FPGA.
给出了一种基于FPGA的等占空比任意整数分频电路的设计方法。
This article introduces the reader to the electronic frequency divider of the two - principles calculation and production.
本文向读者介绍电子分频器二分频的原理计算和制作。
The comparison of digital frequency divider and traditional analog frequency divider shows that the former is more superadded.
比较了数字分频器与传统模拟分频器，说明数字分频器更具优点。
Project 1 will be focused on the design and SPICE simulation of a high speed frequency divider for phase-locked loop applications.
专题1主要是讨论用于相锁迴路应用的高速分频器设计和SPICE模拟。
A novel edge-triggered D-flip-flop based on a resonant tunneling diode (RTD) is proposed and used to construct a binary frequency divider.
提出了一种基于共振隧穿二极管的新型边沿触发d触发器并将之用于构成二进制分频器。
Through analyzing its work principle, we find the method to raise the speed: use a novel CMOS dynamic D flip-flop and an improved synchronous frequency divider.
分析了双模前置分频器的工作原理，提出了提高其工作速度的方法，包括给出一种新型高速CMOS动态D触发器的设计以及同步分频器的改进。
The generator is composed of input shaping circuit, frequency divider circuit, numeric switch phrase shifter circuit, delay second formation circuit, local second formation circuit and so on.
该产生器由输入整形、分频器、数字开关移相器、延迟秒形成、本地秒形成等电路组成。
Design work has also built a system is very particular about the power divider, it has a lower frequency than traditional units in terms of series inductance values.
系统还内置一个设计做工都非常讲究的功率分频器，它有着相对传统而言更低的低频单元串联电感值。
Multi-modulus divider(MMD) based on phase-switching technology finds wide application due to good trade-off between operating frequency and power consumption.
基于相位转换技术的多模分频器由于其在工作频率和功耗中能更好地折中而得到广泛的应用。
A programmable divider used in frequency synthesizer of Rb frequency standard is designed, and the improvement of programmable divider is introduced.
对铷频标中的频率合成器内的程序分频器进行了设计，并介绍了改进后的程序分频器。
High temperature oscillator, divider and inverter produce logic square wave for working frequency so that precise frequency and stable temperature are achieved.
用高温晶体震荡器、分频器和反向器形成新的工作所需的工作频率逻辑方波，以提高工作频率精度和温度的稳定性；
Based on the frequency-domain model of synthesizer, the method can accurately predict the phase noise of the divider and its influence to the phase noise of synthesizer.
这种方法基于频率综合器的频域模型，能比较准确地预测分频器的相位噪声和它对整个频率综合器相位噪声的影响。
By theory analysis of divider transfer function of magnitude-frequency characteristics and phase-frequency characteristics, a new method equalizing stray capacitance could be conclude.
并且通过对分压器传递函数的相频和幅频特性进行理论分析，提出一种分布电容补偿的方法。
Two test methods, both test on boundary scan and test-by-divider, are described in details, especially focusing on the maximum output frequency, the range of output frequency and the time to lock.
分别给出了边界扫描测试和分频器测试两种测试方案，并对两种方案进行了比较，指出了各自的适用范围。
Nc divider design: an adder counter, loading the initial count value, have different frequency output signal of the overflow.
数控分频器设计：对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。
Its internal components available high-frequency and circuit protection with passive divider, high-frequency driver protection circuit to prevent high-overload damage.
其内部部件备有与高频保护电路在一起的无源分频器，高频保护电路可防止高音驱动器过载损坏。
Use a binary digital shifter replace the traditional divider in ADPLL, make the structure simple and keeps the loop gain constant when the frequency multiplication factor changes.
采用数字移位器替代传统的除法器，使得电路结构大大简化，而且在很大的倍频系数范围内都保持很好的稳定性。
The second local frequency signal is provided by an integer-divider after PLL output.
二次变频的本振信号由PLL的输出信号经整数分频得到。
The second local frequency signal is provided by an integer-divider after PLL output.
二次变频的本振信号由PLL的输出信号经整数分频得到。
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