FIG. 3 is a timing diagram that illustrates an example of a minimum pulse width in the DN output signal of a phase frequency detector, according to an embodiment of the present invention.
图3是依照本发明实施例的时序图，其图示说明相位频率检测器的DN输出信号中最小脉冲宽度的示例。
This integrated circuit control the frequency and pulse width of the high voltage IC output signal conveniently by adjusting the input date of IC digital input port.
该集成电路通过对数字输入端口的输入数据的调节，灵活的控制了高压开关集成电路输出信号的频率和脉宽。
This integrated circuit control the frequency and pulse width of the high voltage IC output signal conveniently by adjusting the input date of IC digital input port.
该集成电路通过对数字输入端口的输入数据的调节，灵活的控制了高压开关集成电路输出信号的频率和脉宽。
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