It also give an improved method for PLL (phase locked loop) to extract coherent carrier.
本文还对相干载波提取中的锁相环提出了一种改进方法。
The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.
定量分析了数字式锁相倍频器输出信号的相位抖动。
Now the full integrated PLL (phase locked loop) chip is used widely in radio frequency circuit.
全集成锁相环芯片目前在射频电路中应用很广泛。
An automatic accurate synchronization control scheme which adopts phase locked loop principle is presented.
利用锁相环路原理提出锁相自动准同期控制方案。
Anovel approach to implement symbol timing recovery is presented which USES a hybrid digital phase locked loop (HDPLL).
本文介绍了一种利用混合数字锁相环(HDPLL)实现码元定时恢复的新方法。
A novel all-digital phase locked loop (PLL), applied to the carrier synchronization of communication systems, is designed.
设计了一种用于通信系统载波同步的新数字锁相环。
In this dissertation, theory, model, design and implementation of charge pump phase locked loop frequency synthesizer are lucubrated.
本文围绕电荷泵频率合成器的理论、模型、设计和实现，进行了深入的研究。
Then presented the basic structure, phase model, frequency response and performance analysis for noise and spur, of phase locked loop (PLL).
然后介绍了锁相环(PLL)的基本结构、相位模型、频率响应、噪声及杂散性能。
To aim at the defect of traditional sampled data acquisition scheme, a new method of realizing sampled data acquisition by phase locked loop is presented.
针对传统的取样式数据采集方案存在的缺点，提出一种利用锁相环实现取样式数据采集的新方法。
In the process of signal digital intermediate-frequency received, digital down convertion, frequency tracking of carrier and phase locked loop are the keys.
在信号的中频数字接收过程中，数字下变频、载波频率与相位跟踪是设计的关键所在。
The basic principle of phase locked loop (PLL) has been introduced, and the transmission function of the phase noises of every part of PLL has been analyzed.
介绍了锁相环的基本原理，分析了锁相环各部分电路相位噪声的传递函数。
High precise measuring and tracking of carrier frequency-deviation is necessary to the realization of a high performance phase locked loop in carrier recovery.
载波恢复中高精度的频偏检测与跟踪是高性能锁相位环路实现的必要条件。
This paper gives an analysis of parasitic frequency deviation in the digital phase locked loop, which is one of the important specifications of modern communication systems.
本文分析了数字锁相环路的寄生频偏，它是现代通讯系统中频率合成器的重要指标之一。
Because of the fading characteristic in troposcatter channel, the mechanism of traditional phase locked loop is difficult to achieve the effect in troposcatter communication.
由于对流层散射信道存在严重的衰落现象，故而传统的锁相环机制在散射通信中往往难以奏效。
The primary factor affecting fast phase lock is analyzed by using MATLAB. Then a fast all digital phase locked loop with a high precision automatic modulus control is proposed.
应用MATLAB分析了影响锁相环快速锁定的主要因素，提出了一种具有高精度自动变模控制的快速全数字锁相环。
The principle of voltage linear digital triggering of thyristor by EPROM is described and it is discussed to solve the frequency disturbance on digital trigger by phase locked loop .
描述了用EPROM实现晶闸管电压线性触发原理，讨论了用锁相环解决数字触发的频率扰动问题。
According to transfer functions of the loop filter and the single phase locked loop system, it figures out the loop filters parameters, and introduces the selection of loop bandwidth.
根据环路滤波器传递函数以及单环锁相系统的传递函数，计算出环路滤波器的各个参数，并介绍了环路带宽的选择。
The operating principle and performance of fractional-N phase locked loop (FNPLL) are described in detail, and the methods of suppressing FNPLL phase modulation sideband are introduced.
较详细介绍了分数分频锁相环的工作原理和特性，以及抑制分数分频锁相环相位调制边带的方法。
Phase locked loop technique offers a way to resolve this problem.
锁相式频率合成技术提供了解决这一问题的思路。
With the signal from the master clock, the slave clock is able to recover an accurate local clock signal using a Clock Recovery Phase Locked Loop (PLL).
从时钟利用主时钟发来的时钟信号，通过数字锁相环恢复出本地时钟信号。
Through debugging the hardware circuit of the Phase Locked Loop and writing the Single-Chip Processor program, a good performance frequency source is realized.
通过对锁相环硬件电路的调试和编写相关单片机控制程序，实现了一个性能较好的频率源。
Second, an Enhanced Phase Locked Loop (EPLL) control strategy based on improved Adaptive Notch Filtering (ANF) is proposed, controller parameters are optimized using BF-PSO algorithm.
其次，提出了一种基于改进型ANF的三相EPLL控制策略，并用BF-PSO算法对控制器参数进行优化设计。
In phase-coherent communication system, phase-locked loop is always used to yield coherent reference signal.
相位相干通信系统中，通常采用锁相环路来产生相干参考信号。
The phase- locked loop is one kind of control system which is able to achieve phase automatic lock, to compose frequency and to trace demodulation system.
锁相环路是一种能实现相位自动锁定的控制系统，主要用于频率合成及跟踪解调系统。
This paper discusses an all digital phase-locked loop with a zero-crossing detector and a loop filter.
本文讨论的全数字锁相环包括过零检测器和环路滤波器。
The design of precise position tracking loop for DRTS with fast digital phase-locked loop is described.
本文提出一种用于光盘径向伺服系统的带有快速数字锁相环的精密位置跟踪环路的设计方案。
It USES a high precision digital phase-locked loop (PLL) to accurately recover the Synchronous reference information of raw cloud-cover image data collected by the geostationary satellite.
它用高精度数字锁相环，精确地恢复地球同步气象卫星采集的原始云图数据的同步基准信息。
The use of phase-locked loop technology makes the sampling frequency synchronously follow the signal frequency and improves the calculation accuracy of sampling data.
运用锁相环技术使采样频率同步跟踪信号频率，提高采样数据计算的准确性。
A fast all digital phase-locked loop with automatic modulus control is presented.
提出了一种具有自动变模控制的快速全数字锁相环。
A fast all digital phase-locked loop with automatic modulus control is presented.
提出了一种具有自动变模控制的快速全数字锁相环。
应用推荐