The timing error detector and loop filter of HDPLL are all digitized, whereas the VCXO employs analog components.

HDPLL中定时误差检测器、环路滤波器是全数字的，而VCXO使用了模拟器件。

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The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.

环路为反馈结构，包括插值器、时钟误差检测和环路滤波器三个部分。

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Simulation results show that the new detector has a lower packet detect error rate and a higher symbol timing precision compared with the existing schemes.

仿真结果表明，与已有的分组检测算法相比，新方法具有更低的分组检测错误概率，同时也改善了符号精定时的精度。

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Simulation results show that the new detector has a lower packet detect error rate and a higher symbol timing precision compared with the existing schemes.

仿真结果表明，与已有的分组检测算法相比，新方法具有更低的分组检测错误概率，同时也改善了符号精定时的精度。

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