An on-resistance self limitation 2-d model for integrated power devices with buried layer is proposed.
对具有埋层结构的集成大功率器件提出了导通电阻自限制二维模型。
A buried layer (7) is provided as a collector connection area which joins the collector contact (6) to a collector area (14).
埋层(7)作为集电极连接区域提供，用于连接集电极接触(6)和集电极区(14)。
Using the derived amplitude and phase expressions, the experimental data of the three-layer sample are fitted. The thickness of the buried layer in the sample is calculated.
用推导的振幅和位相表达式拟合三层样品的实验数据，并计算出中间层的厚度。
For isolated LDMOS devices, the resistance between the lateral isolation wall (32) (tied to the source) and the buried layer (24) is reduced, thereby reducing substrate injection current.
对于隔离的LDMOS器件，横向隔离壁(32)(结合至源极)与埋层(24)之间的电阻减少，从而减少了衬底注入电流。
The soft soil subgrade treatment should be adopted different measures according to the physical and chemistry characteristics of soft soil, buried layer depth, material condition and road.
软土路基处理应根据软土、淤泥的物理力学性质、埋层深度、材料条件、公路等因素分别采取处理措施。
We try to obtain the common-base current gain a of the parasitic PNP transistor from the eloping profile of the collector region including the effect of buried-layer.
本文从包括埋层影响的集区杂质分布出发，求出了寄生PNP晶体管的共基极电流放大系数。
We try to obtain the common-base current gain a of the parasitic PNP transistor from the eloping profile of the collector region including the effect of buried-layer.
本文从包括埋层影响的集区杂质分布出发，求出了寄生PNP晶体管的共基极电流放大系数。
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