This is because process execution now needs to be coordinated across the bus, which operates at half the clock frequency of the chip.
这是因为进程执行现在需要跨总线协调，以一半的芯片时钟频率进行处理。
NRZ code doesn't contain synchronous clock frequency.
它本身不含有位同步时钟分量。
Best frequency relation is given between IF coherent oscillating source and clock frequency of full coherent radar.
给出了全相参雷达频率源的中频相干振荡源及时钟频率之间的最佳频率关系。
This article mainly addresses the maintenance period of clock frequency of SPC exchanges in China's telecommunication network.
本文主要讨论我国电信网中程控交换局时钟频率维护周期的确定问题。
In this case, the crystal oscillator can not provide a stable clock frequency, which results in the abnormality of the device.
在这种情况下，晶体振荡器就不能为设备提供稳定的时钟频率，导致设备工作异常。
The external clock frequency applied to the AD7764 determines the sample rate, filter corner frequencies, and output word rate.
AD7764的采样速率、滤波器转折频率和输出字速率由外部时钟频率决定。
The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7763.
采样速率、滤波器转折频率和输出字速率由AD7763的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7762.
采样速率、滤波器转折频率和输出字速率由ad7762的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies, and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7760.
采样速率、滤波器转折频率和输出字速率由ad7760的外部时钟频率与配置寄存器共同设置。
Clock Tree Synthesis is important in the backend-end design of chip design, and the clock skew has become the major part of constraints that limit system clock frequency.
时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。
The sample rate, filter corner frequency, settling time, group delay and output word rate will be reduced also, as these are proportional to the external clock frequency.
由于采样速率、滤波器转折频率、建立时间、群延迟和输出字速率与外部时钟频率呈比例变化关系，因此这些参数也会相应降低。
In deep submicron era, IC design in physical design has more and more challenge, with the increasing design scale, faster clock frequency and minimizing process dimension.
在深亚微米时代，随着设计规模变大，时钟频率越来越高以及工艺尺寸的减小，IC物理设计面临着诸多困难。
The higher the clock frequency is, the more PLL influences the performance of microprocessors. PLL technique has been one of the core techniques in modern microprocessor design.
随着时钟频率的不断提高，微处理器的性能受锁相环的影响越来越大，锁相环技术已经成为当代微处理器的核心技术之一。
The capacity and speed of the memory subsystem in this architecture can be improved using the existed memory devices while the cost can be downgraded without enhancement of the clock frequency.
该结构可利用现有存储器件在不增加时钟频率的情况下，提高存储器系统的容量和速度，同时降低成本。
Meanwhile, the switched capacitor notch filter is designed, which can adjust center frequency freely by changing the switching clock frequency and make the center frequency highly accurate and stable.
介绍了数字化开关电容滤波技术，并设计了可以通过改变开关时钟频率来自由调整中心频率的开关电容带阻滤波器，使中心频率具有很高的精度和稳定度。
Meanwhile, the switched capacitor notch filter is designed, which can adjust center frequency freely by changing the switching clock frequency and make the center frequency highly accurate and stable.
介绍了数字化开关电容滤波技术，并设计了可以通过改变开关时钟频率来自由调整中心频率的开关电容带阻滤波器，使中心频率具有很高的精度和稳定度。
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