The irredundant sorting bus encoding method reduces the power dissipation of highly capacitive memory address bus based on the dynamic reordering of the modified offset address bus lines.
提出了一种新的低功耗非冗余排序总线编码方法，通过对改进的偏移地址线的动态重排以降低具有高负载的地址总线的功耗。
The address bus is used by the processor to select aspecific memory location or register within a particular peripheral.
地址总线被处理器用来选择在特定外设中的存储器地址或寄存器。
A memory address consists of binary data being output on an appropriate bus which we call the address bus.
一个存储器地址是由输出到适宜的总线上的二进制数据所组成。这个总线我们称为地址总线。
The actual address that is placed on the address bus when accessing a memory location or register.
当访问内存位置或寄存器时，在地址总线上的真实的地址。
Thee actual address that is placed on the address bus when accessing a memory location or register.
当访问内存位置或寄存器时，在地址总线上的真实的地址。
Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory.
端口0也是复低位地址和在利用外部程序和数据存储器的数据总线。
A "real" address the value that must be placed on the system address bus to select a physical memory bank or device.
物理地址：真实的地址，其值必须被置于系统地址总线中用于选择物理存储位置或者设备。
To a micro-controller, the PDIUSBD12 appears as a memory device 8-bit data bus and 1 address bit (occupying 2 locations).
对微控制器而言，PDIUSBD12看起来就像一个带8位数据总线和一个地址位（占用两个位置）的存储器件。
The address bus specifies the memory locations (addresses) for the data transfers.
地址总线为数据传输指明内存位置(地址)。
The address bus is used by the processor to select a specific memory location or register within a particular peripheral.
地址总线被处理器用来选择在特定外设中的存储器地址或寄存器。
The MSI memory location is a physical bus address, so it must be translated to virtual address space both on device and host.
MSI的内存位置的物理地址，所以它必须转换为对设备和主机的虚拟地址空间。
The memory system of dual channel A/D automatic acquisition is studied in this paper. Using transceivers and gating controllers, the data bus and address bus of RAM are respectively controlled.
本文研究了双通道A/D自动采集存储系统，利用数据收发器及数据选通控制器分别控制RAM的数据线及地址控制线。
The memory system of dual channel A/D automatic acquisition is studied in this paper. Using transceivers and gating controllers, the data bus and address bus of RAM are respectively controlled.
本文研究了双通道A/D自动采集存储系统，利用数据收发器及数据选通控制器分别控制RAM的数据线及地址控制线。
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