The VHDL program embedded in the FPGA chip includes: interface combine ISA bus and FPGA, serial asynchronous communication module for transmitting and receiving.
该接口卡FPGA芯片内部VHDL程序含：ISA总线与FPGA接口、串行异步通信发送及接收模块。
The program is compiled with VHDL(hardware description language).
试验程序由VHDL硬件描述语言编写。
Lastly, the hardware circuit, VHDL program design and debugging methods based on FPGA are discussed.
最后对基于现场可编程门阵列(FPGA)的硬件电路、VHDL语言程序设计及调试方法进行了讨论。
The paper brought forward simulation tactic of complex numeral system, designed VHDL testing basic program and finished simulation validation of system function blocks.
本文提出了复杂数字系统的模拟策略，设计了VHDL测试基准程序，完成了系统功能模块的模拟验证。
This program is designed with VHDL, the traffic light controlled T-junction circuit.
本程序是用VHDL语言设计的丁字路口的交通灯控制电路。
On the side of software, the design method of control program completed with language VHDL is provided.
软件方面给出了用VHDL语言编写控制程序的设计思路；
Based on FPGA the equipment with the functions of asynchronous serial data transfer, self-test capability, fuze product test and so on is designed and realized by VHDL program.
该设备以FPGA为核心，使用VHDL硬件描述语言设计并实现了异步串行通讯、测试设备的自检、引信产品的检测等几大功能。
Complex program logic device (CPLD) has been chosen as the hardware design platform, driving schedule generator has been described with VHDL.
选用复杂可编程器件(CPLD)作为硬件设计载体，使用VHDL语言对驱动时序发生器进行了硬件描述。
This paper mainly introduces the common principles of RISC microprocessors design and the internal structure, and the way to program the VHDL software of hardwired control unit.
文中主要介绍了RISC微处理器设计遵循的一般原则，RISC模型机的内部结构设计原理及硬联线控制器的VHDL软件设计方法。
A design method by usage of finite state machine and VHDL hardware description language to develop the program is adopted, then it is simulated and downloaded on the EDA software platform.
采用有限状态机设计方法，使用VHDL硬件描述语言编程，并在EDA工具软件平台上进行了仿真和下载。
VHDL program design and testing of the adaptation module;
提出了以太网业务接入的实验节点设备设计方案。
There square, triangular wave of the different VHDL program.
还有方波，三角波的不同的VHDL程序实现。
The system utilizes data-chosen-switches, microprocessor AT89C51 and complex logic device (CPLD). The software program is written by C language and VHDL language, respectively.
该系统数字部分主要利用拨码开关、单片机AT89C51，复杂可编程逻辑器件进行设计。
This paper researched the work theory and structure of traditional BERT, and used VHDL program language to realize a majority of BERT functions on FPGA.
本设计研究了传统误码仪的工作原理与结构，并利用VHDL语言在FPGA芯片上模拟实现了绝大部分的传统误码仪的功能。
This paper researched the work theory and structure of traditional BERT, and used VHDL program language to realize a majority of BERT functions on FPGA.
本设计研究了传统误码仪的工作原理与结构，并利用VHDL语言在FPGA芯片上模拟实现了绝大部分的传统误码仪的功能。
应用推荐