A GPU is a hardware coprocessor that accelerates computations for computer graphics applications.
GPU是一种硬件协处理器，可加速计算机图形应用程序的计算。
The FPGA was used as a coprocessor for image acquisition and pre-processing.
FPGA作为协处理器完成图像的采集和预处理。
This paper designs a RSA crypto-coprocessor based on the research of RSA cryptographic algorithm.
本文在对RSA密码算法研究的基础上，进行了RSA密码处理器的设计。
In order to improve the performance of the coprocessor, a new passing way of the address generator is designed.
为了提高协处理器的性能，地址产生器中设计了新的传送路径。
The address generator mainly implements the address calculation and instruction-field extraction of the coprocessor.
该地址产生器主要完成地址计算和协处理器指令的场抽取功能。
The area and speed of cryptography coprocessor impede the application of public-key cryptography RSA for smart card.
密码协处理器的面积过大和速度较慢制约了公钥密码体制RSA在智能卡中的应用。
An approach of Micro program Controller design for coprocessor is put forward and a test bench is given to verify its function.
在微程序控制器的设计中提出一种协处理器微程序控制器的设计方法，并且给出其功能验证的测试平台。
The components are modules that construct the reconfigurable cipher coprocessor, and the structure is their connection network.
可重构密码协处理器组成与结构是指可重构密码协处理器的组成模块及其相互之间的连接网络。
This paper forwards a hardware solution based on NP and coprocessor which could be used in matching and lookup in application layer.
文章提出了一种基于网络处理器及应用层匹配查找协处理器的硬件解决方案，来实现高速网络环境的入侵检测。
This paper presents an embedded monocular vision system for object tracking in real time with coprocessor architecture based on DSPand FPGA.
提出了一套基于DSP/FPGA的协处理器结构用以实现实时目标跟踪的嵌入式视觉系统。
The control interface module shields the various differences of the main processor, which improves the portability of the coprocessor system.
通过系统中控制接口模块接收主处理器发送的控制指令，屏蔽了不同主处理器之间的差异，增强了系统的可移植性。
High-Speed Floating-point Adder is a critical part in the coprocessor, which is attached to the computing basis of floating-point instructions.
浮点加法器是协处理器的核心运算部件，是实现浮点指令各种运算的基础，其设计优化是提高浮点运算速度和精度的关键途径。
At last, a new technique that PLD as a coprocessor works together with DSP chip in the complex data processing of intelligent fuze is put forward.
最后，提出了在人工智能引信复杂数据处理任务中PLD作为协处理器与DSP处理器结合使用的新的技术途径。
Based on the reconfigurable computing system, the thesis proposes RAC, a reconfigurable array coprocessor model, targeted at multimedia image applications.
本论文基于可重构计算系统提出了针对多媒体图像处理的可重构阵列协处理器模型RAC。
The block cipher coprocessor has been applied in a PCI-FPGA cipher card designed by the Information Security Technology Laboratory of Guangzhou University.
分组密码协处理器现已成功的应用到了广州大学信息安全技术实验室研制的PCI - FPGA密码卡中。
Considering the marketing requests for reducing the low cost of the processor, this paper optimizes the executable solution for the RSA crypto-coprocessor.
在总结前人的算法的基础上，充分考虑了处理器大规模应用的低成本要求，提出了可行的RSA密码处理器的算法解决方案。
An area efficient modular arithmetic processor was developed that is capable of performing RSA public-key cryptography and other modular arithmetic operations as a coprocessor.
为以较小的面积代价实现RSA公钥密码算法及其他一些算法所需的求模、模加、模乘、模幂等运算，该文设计了一种可作为协处理器使用的模运算处理器。
Combined with the design of a math coprocessor, the paper dis-cusses how to determine microinstruction format and write microgram code. Multiplication code is presented as an example.
文章以某数值协处理器的设计为例，研究了微指令格式的确定以及微程序代码的编写，并给出了编制的乘法微代码的实例。
This dissertation's focus is on the investigation of the design and implementation of real-time multi-target capture module and distance operation coprocessor, which are implemented with FPGA.
本文重点研究了基于FPGA的实时多目标捕获模块和距离运算协处理器的设计与实现。
The ICA device is modeled after the shallow firmware mode of the 4758 Coprocessor.
ICA设备是照4758Coprocessor的shallow固件模式建模的。
The ICA device is modeled after the shallow firmware mode of the 4758 Coprocessor.
ICA设备是照4758Coprocessor的shallow固件模式建模的。
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