The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.
定量分析了数字式锁相倍频器输出信号的相位抖动。
The principles, design method and process of PHEMT frequency doubler are presented particularly.
其中重点论述了有源倍频器的工作原理、设计方法以及详细的设计过程。
The clock signal is obtained by using a frequency doubler which USES a modified XOR topology, so that the complexity of the system is reduced.
改进异或门拓扑结构实现的二倍频器，结构简单、实用，降低了电路复杂度。
To solve the problem of exaggerated angle pulse in the ratio driving and tracing measuring technique in testing in situ for large gears, the programmable dynamic frequency doubler has been developed.
为解决大齿轮在机测量过程中采用比例驱动跟踪测量技术时转角脉冲当量过大的问题，研究开发了可编程动态倍频器。
To solve the problem of exaggerated angle pulse in the ratio driving and tracing measuring technique in testing in situ for large gears, the programmable dynamic frequency doubler has been developed.
为解决大齿轮在机测量过程中采用比例驱动跟踪测量技术时转角脉冲当量过大的问题，研究开发了可编程动态倍频器。
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