No CPU is needed for the fuzzy controller circuit. All algorithms are realized for high speed by digital logic circuits.
该模糊控制器电路不用cpu，全部算法由数字逻辑电路实现，具有运算速度快的特点，适合于需要高速控制的场合。
The design method of LED big screen scanning circuit is introduced, and the virtues of programmable logic device application on high-speed digital system are presented.
介绍了LED大屏幕扫描电路的设计方法，阐述了可编程逻辑器件在高速数字系统应用中的优点。
The feature of rapidly develop, high speed and high reliability of Complex Program Logic Device(CPLD) makes CPLD playing a more and more role in the design of digital system.
大规模可编程逻辑阵列（CPLD）的快速开发、在系统编程以及高速可靠的特点使得CPLD在数字系统的构建中起到越来越重要的作用。
FPGA is used to achieve the complex and high-speed logic control and the design of time sequence, with grabbed digital video signal cut and stored in SRAM, under the principles of the video signal.
利用FPGA完成复杂且高速的逻辑控制及时序设计，将采集的图像根据视频信号原理进行裁剪并存储在SRAM中。
On this basis, the principle prototype is developed with high speed digital signal processor (DSP), the huge reprogrammable logic gate arrays (FPGA) and real-time software.
在此基础上，采用高速数字信号处理器、大规模可编程逻辑门阵列和实时软件进行系统设计，完成了原理样机的研制。
Use the high-performance programmable logic device (CPLD) to realize the control of the digital circuit at high speed;
使用高性能的可编程逻辑器件（CPLD）实现高速数字电路的控制；
At high speeds, logic signals often appear hairy, jagged and distorted because of fast signal rise and fall time. We must avoid these phenomena in the high-speed digital circuit system.
数据速率的提高导致数字信号的上升沿和下降沿时间不断缩短、脉宽变窄和周期减小，从而使数字信号在传输过程中出现毛刺、扭曲和扩展等畸变现象。
At high speeds, logic signals often appear hairy, jagged and distorted because of fast signal rise and fall time. We must avoid these phenomena in the high-speed digital circuit system.
数据速率的提高导致数字信号的上升沿和下降沿时间不断缩短、脉宽变窄和周期减小，从而使数字信号在传输过程中出现毛刺、扭曲和扩展等畸变现象。
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