The interrupt controller hardware sends interrupts to any CPU.
中断控制器硬件可以将中断发送到任何CPU。
The interrupt controller hardware needs to recognize the source of the interrupt and which partition should receive that interrupt.
中断控制器硬件需要确定中断源，以及应该接收该中断的分区。
In particular, the Cell processor includes an interrupt controller and an IOMMU implementation, both of which are incompatible with those supported by older kernel versions.
具体来说，Cell处理器包括一个中断控制器和一个IOMMU的实现，它们与早期的内核版本的支持都是不兼容的。
The essential hardwares of computer contain CPU, memory, interrupt controller, DMA controller, etc.
计算机硬件的核心器件有CPU、内存、中断控制器、DMA控制器，等等。
It is mainly composed of DMA controller (82c37), interrupt controller (82c59), programmable interval timers (82c54), DRAM refresh control, wait state generator and system reset logic.
其内部主要由DMA控制器(82c37)、中断控制器(82c59)、可编程间隔计时器(82c54)，DRAM刷新控制器，等待状态产生器，系统重置电路组成。
It is mainly composed of DMA controller (82c37), interrupt controller (82c59), programmable interval timers (82c54), DRAM refresh control, wait state generator and system reset logic.
其内部主要由DMA控制器(82c37)、中断控制器(82c59)、可编程间隔计时器(82c54)，DRAM刷新控制器，等待状态产生器，系统重置电路组成。
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