PLS algorithm is presented as a new logic synthesis algorithm for PAL.
本文针对pal器件的分析提出一种新型逻辑综合算法，即pls算法。
Sequential logic synthesis is an important part of RTL synthesis system design.
时序逻辑综合是RTL综合系统设计中的一个重要部分。
Optimization in automatic logic synthesis is usually done after the Boolean equations are set up.
逻辑自动综合中控制部分的优化一般是在布尔方程确定之后进行。
In the area of logic synthesis, a procedure of derivation of complements for a given product set is frequently used.
在逻辑综合的领域内，经常使用求给定积项集合补集的过程。
Verification and logic synthesis result show that the DDC chip can meet the requirement, also have stable performance.
验证和逻辑综合结果表明DDC芯片能满足设计要求，性能稳定。
The logic synthesis of VHDL language is a method that the description of higher abstract hierarchy is shifted to lower one automatically.
VHDL语言的逻辑综合就是将较高抽象层次的描述自动转换到较低抽象层次描述的一种方法。
The test results show that the developed logic synthesis subsystem can accomplish the cosmic data set processing rapidly and efficiently.
经测试结果表明，基于子集迭代相交算法的逻辑综合系统能够快速、有效的完成大规模数据集合的逻辑综合处理。
Recent years, being one of the most difficult problems, automatic logic synthesis for large scale PLDs has gained more and more attention.
大规模集成PLD器件的逻辑综合是近年来引起广泛关注的热点和难点问题。
The reference CPU core use VHDL language input, make logic synthesis and simulation through the popular EDA tools, then it was implemented in FPGA.
CPU内核采用VHDL硬件描述语言输入，结合流行的EDA设计、综合、仿真工具，最后在FPGA上实现该内核。
Functions of logic synthesis are to transform and optimize the combinational logic functions and produce the pure logic level structural description.
逻辑综合的功能是对组合逻辑函数的描述进行转换和优化，生成与逻辑功能描述等价的优化的逻辑级纯结构描述。
In logic verification and logic synthesis, Boolean matching is widely used to testify whether two given functions are logically equal by means of OBDD.
在逻辑验证和综合中，布尔匹配利用有序二叉判定图obdd来检验两个给定的逻辑函数是否相等。
As for non-threshold function, a novel logic synthesis algorithm is proposed, which can transform non-threshold function to the sum of some threshold functions.
对于非阈值函数，该文提出了新的逻辑函数综合算法，可以将任意非阈值函数转化为几个阈值函数和的形式。
The above work is intended to set up an automatic logic synthesis system to translate a register transfer level language descriptions into hardware logic diagrams.
上述工作是为了建立一个将寄存器传输级语言描述翻译成硬件逻辑图的自动逻辑综合系统。
This paper deals with the design and realization of logic synthesis system from behavioural description to structure description developed by DA Lab. of Beijing Institute of Technology.
本文详述了北京理工大学DA实验室开发的从行为功能级描述到结构描述的自动综合系统的设计与实现。
Experiment results show that this approach can efficiently reduce area of logic synthesis results compared with the traditional clock skew scheduling algorithm, without degrading the performance.
实验结果表明：按权重分配裕量的方法相对于平均分配裕量，能够在不降低电路性能的情况下，更加有效地降低逻辑综合结果的面积。
Experiment results show that this approach can efficiently reduce area of logic synthesis results compared with the traditional clock skew scheduling algorithm, without degrading the performance.
实验结果表明：按权重分配裕量的方法相对于平均分配裕量，能够在不降低电路性能的情况下，更加有效地降低逻辑综合结果的面积。
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