This paper develops a hardware architecture of the multi-standard loop-filter that can be used for both standards in various codec systems.
本文的工作就是设计一种支持这两种标准编解码的环路滤波器硬件架构，并对其进行验证和性能分析。
In fact, Scala's Enumeration class supports the usual methods for working with collections, so we can easily iterate through the breeds with a for loop and filter them by name.
实际上，Scala的枚举类支持和集合协作需要的一般方法，所以我们可以简单地在循环中遍历这些种类，或者通过名字过滤它们。
The timing error detector and loop filter of HDPLL are all digitized, whereas the VCXO employs analog components.
HDPLL中定时误差检测器、环路滤波器是全数字的，而VCXO使用了模拟器件。
In this article, PLL theory, design of loop filter and phase noise theory are introduced at first.
本文先介绍了锁相环的工作原理，环路滤波器的设计并对相位噪声的理论进行了阐述。
Then analyses the complexity of AVS decoder and finds out the the critical modules are motion compensation, integer transform, quantization and loop filter.
然后对解码器进行复杂度分析，找出解码耗时的关键部分分别为运动补偿、反变换、环路滤波等模块。
Noise which comes from both active and passive circuit element in loop filter will deteriorate phase noise of output signal.
环路滤波器中的有源和无源器件均有噪声产生，此类噪声会叠加在输出信号上，从而恶化输出信号的相位噪声。
Because of the frequency lock loop traction PLL filter can be designed very narrow, with very good noise suppression performance, to meet the precise requirements of carrier phase tracking.
由于有锁频环的频率牵引，锁相环路滤波器可以设计得很窄，具有很好的抑噪性能，满足精确跟踪载波相位的要求。
The output amplitude and the length of pulses train are greatly improved with additional semiconductor optical amplifier and filter in the optical fiber loop as the DC component of input keeps low.
光纤环形腔中光放大器、滤波器的加入，以及光脉冲直流基座的降低，可以明显改善输出的幅值和复制序列长度。
Because the circuit needs current overload protect, a double loop strategy , with current feedback of filter inductance as inner loop and output voltage as outer loop, is studied.
根据需要电路电流过流保护的特点，重点介绍了滤波电感电流反馈做内环，输出电压做外环的双环控制策略。
This implements a tiny benchmark for a FIR filter loop using a C version, and a NEON-optimized one for devices that support it.
它实现了一个使用C版本的FIR（注：有限脉冲响应）滤波器循环，以及针对支持硬件NEON的设备的经过NEON优化的小型性能比较测试。
The possibility of using this kind of phase-locked loop under noise interference and the problems of filter design are discussed.
文中还讨论了在噪声作用下采用这种环路的可能性和滤波器的设计问题。
The method of designing the loop filter with the phase margin and loop bandwidth is displayed.
并提出了从环路带宽和相位余量出发设计环路滤波器的方法。
The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.
环路为反馈结构，包括插值器、时钟误差检测和环路滤波器三个部分。
According to transfer functions of the loop filter and the single phase locked loop system, it figures out the loop filters parameters, and introduces the selection of loop bandwidth.
根据环路滤波器传递函数以及单环锁相系统的传递函数，计算出环路滤波器的各个参数，并介绍了环路带宽的选择。
This paper gives the design and experimental results of low noise NPLL frequency synthesizer and concludes that the passive loop filter is more suitable for low noise design than active loop filter.
介绍低相噪NPLL频率综合器的设计及实验结果。提出用无源环路滤波器比用有源环路滤波器更好，可获得低相噪设计。
The paper analyzes the design method of passive loop filter thoroughly, and presents a effective design method. The method has obvious advantage comparing to the design method in existence.
对锁相环的环路滤波器的设计方法进行了深入研究，给出了一种环路滤波器设计方法，该设计方法与现有设计方法相比具有较明显的优点。
The narrower the loop filter bandwidth the smaller the achievable phase error. This comes at the expense of slower response and reduced capture range.
滤波器的带宽越窄，得到的相位差越小，其代价为响应变慢俘获范围变小。
Loop filter: the encoder attempts to optimize the loop filter parameters for maximum PSNR.
回放过滤器：编码器试图优化回放过滤器的参数，以达到最大的峰值信噪比。
A passive loop filter scheme and the design method of the filter for current charge pump PLL frequency synthesizer chip are given in the paper.
针对电流型电荷泵PLL频率综合器芯片，提出一种称为极值相位裕量的无源环路滤波器方案和设计方法。
When the PFD does not generate pulses in lock mode, the charge pump does not provide charge to the loop filter.
当PFD在锁定模式中不生成脉冲时，电荷泵不提供电荷给环路滤波器。
Thirdly, interpolation equation, polynomial interpolation filter and interpolation control for timing adjustment are studied. The performance of interpolation loop is simulated.
最后针对定时调整算法，研究了插值等式、多项式插值滤波器及插值控制，模拟了插值环路的性能。
The function of a loop filter is to filter high-frequency signal out of the output voltage from PFD and CP, thus the output signal from VCO will be purified.
环路滤波器的作用就是滤除从PFD&CP出来的电压中的高频成分，从而纯化VCO的输出信号。
Active band-pass filter is a important section of pulse width modulated rebalance loop.
有源带通滤波器是脉冲调宽再平衡回路的一个重要部分。
This paper discusses an all digital phase-locked loop with a zero-crossing detector and a loop filter.
本文讨论的全数字锁相环包括过零检测器和环路滤波器。
The method of erbium-doped fiber amplifier(EDFA) gain flattening using a fiber loop mirror(FLM) acting as a wavelength filter was analyzed in theory.
从理论上分析了利用光纤环形镜（FLM）中的偏振耦合效应作为滤波器，对掺铒光纤放大器（EDFA）实现增益平坦化的方法。
Experiments demonstrate that L-band EDFA will achieve high flat gain by employing a gain flat filter based on fiber loop mirror (FLM).
使用光纤环形镜(FLM)作为增益平坦滤波器进行L波段掺铒光纤放大器的增益平坦化实验，实现了高增益值的平坦输出。
Upon the low power design consideration, a hybrid active-passive loop filter is employed and the signal summing block is removed by using discrete-time differentiation technique.
基于低功耗设计考虑，调制器采用有源-无源混合型环路滤波器，并通过离散时间微分技术移除信号求和模块。
This paper presents a simple tracking filter circuit, which is applicable to Doppler radar sets and consists mainly of a switched bandpass filter and a phase-locked loop.
本文提出一种简单的跟踪滤波器电路，该电路可用于多普勒雷达，主要由开关式带通滤波器和锁相环组成。
Digital PLL and digital filter are built based on conventional double closed-loop control which contains voltage loop and current loop.
前者在常规的采用电压外环、电流内环的双闭环控制基础上，搭建数字锁相环、数字滤波器。
Microstrip dual-mode bandpass filter with novel rectangular-loop has been studied in this dissertation to realize miniaturized broadband bandpass filter which is easy to adjust.
基于这一背景，本文主要研究基于新型微扰小环的微带双模滤波器技术，目的是得到调试灵活的小型化宽带带通滤波器。
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