A portion of the buffer cycle in which the logic or arithmetic unit must cease operation or neither will be able to communicate with the memory unit.
缓冲存储器周期的一部分，在这期间，逻辑与算术运算器必须中止操作或不能与存储器传输信息。
The improved model of input buffer presented is to insert a quasi random memory between input queue and arbitration logic at ATM switching unit.
改进的输入缓冲方案是在AT M交换单元的输入队列和仲裁逻辑之间加入一个准随机存储器。
The crucial path includes address buffer, decoder, memory unit, sense amplifier and output buffer.
其中包括地址缓冲、译码器、存储单元、灵敏放大器和输出缓冲电路。
The FPGA is designed as a MVB controller which consists of Manchester encoder, Manchester decoder, buffer, center control unit, internal memory, MCU interface and so on.
FPGA实现MV B控制器功能，分为曼彻斯特编码器、解码器、缓冲区、中央控制单元、内部存储器和单片机接口等几部分。
Based on the single buffer copy technology, the strategy overcomes the inefficiency of storage block copy in some embedded system's memory control unit.
该策略基于缓冲区单次拷贝技术，克服了有些嵌入式系统存储控制器低效的存储块拷贝。
Based on the single buffer copy technology, the strategy overcomes the inefficiency of storage block copy in some embedded system's memory control unit.
该策略基于缓冲区单次拷贝技术，克服了有些嵌入式系统存储控制器低效的存储块拷贝。
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