This register defines the physical serial interface which will be used for data communications.
这个寄存器定义了将用于数据通信的物理串行接口。
Serial communications based on SERDES adopt the clock_data recovery(CDR) instead of both data and clock transmitting, which solve the problem of clock skew.
基于SERDES的串行通信过程中采用时钟和数据恢复技术（CDR）代替同时传输数据和时钟，从而解决了限制数据传输速率的信号时钟偏移问题。
Under this background, this paper designs the system from data collection to test results representation, which includes drawing voyage chart, GPS serial port communications and user interface.
在此背景下，本文设计并实现了包括航迹图展示、GPS串口通信以及人机界面三个子系统的从数据采集到试航结果展示的完整的测试系统。
Modems used for the entire time series FPGA control, the use of DSP to CMB909 executable program control, data and images of the packaging and communications between PC machine and serial interface.
整个调制解调器采用FPGA进行时序控制，采用DSP对CMB909进行编程控制、数据帧的打包以及和PC机的串口通信。
Modems used for the entire time series FPGA control, the use of DSP to CMB909 executable program control, data and images of the packaging and communications between PC machine and serial interface.
整个调制解调器采用FPGA进行时序控制，采用DSP对CMB909进行编程控制、数据帧的打包以及和PC机的串口通信。
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