Project 1 will be focused on the design and SPICE simulation of a high speed frequency divider for phase-locked loop applications.
2
数控分频器设计:对于一个加法计数器,装载不同的计数初始值时,会有不同频率的溢出输出信号。
Nc divider design: an adder counter, loading the initial count value, have different frequency output signal of the overflow.
3
系统还内置一个设计做工都非常讲究的功率分频器,它有着相对传统而言更低的低频单元串联电感值。
Design work has also built a system is very particular about the power divider, it has a lower frequency than traditional units in terms of series inductance values.