Clock skew is in a synchronization digital integrated circuit design difficult problem.
2
时钟树的设计是同步数字集成电路设计中的一个重要部分,对系统的性能和可靠性有很大影响。
In designing synchronous digital integrated circuits, the design of clock tree is an important component, which may greatly affect the performance and reliability of the system.
3
基于VHDL的串行同步通信电路设计,包括串行同步发送电路和接收电路的设计。
The circuit design of serial synchronous communication based on VHDL includes design of serial synchronous sending circuit and receiving circuit.