数字抽取滤波器

Digital decimation filter

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digital decimation filter
∑ΔADC由两个主要的部件构成:一个模拟∑Δmodulator(调制器)和一个数字抽取滤波器(digital decimation filter)。数字抽取滤波器的主要作用是滤除可能引起混迭的带外噪声,其次,它能够将前级调制器过采样的高速率数据降低

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数字抽取滤波器是它的重要组成部分，通常采用多级结构来实现。
The digital decimation filter taking the important constituent in the Delta-Sigma Analog-to-Digital converter is realized by the multistage structure.
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根据FPGA芯片的特点，FIR数字抽取滤波器采用分布式算法来实现，这种方法实现的基础是查找表。
According to the character of FPGA, the FIR digital decimation filter is implemented via using distribution algorithms which are based on the technique of looking up table.
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该转换器采用了高阶MASH噪声成形技术，而其数字抽取滤波部分则由梳状滤波器与级联的半带滤波器构成。
The converter USES a high order MASH noise shaping technique and a digital decimation filtering part consisting of comb filters and cascade of half band filters.

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