In building the timing constraints, do you need to constrain all IO ports?
2
研究了并利用PE(处理单元)结构时序约束和加法树结构的加法阵列优化设计性能。
The timing requirements for PE structure and the adder array for adder tree structure to optimize performance of design are studied and used.
3
提出了一种新的时钟偏斜规划算法，该算法所生成的时序约束可以有效地促进逻辑综合工具的面积优化。
A new clock skew scheduling algorithm is proposed. This algorithm generates timing constraints which can effectively promote the area optimization of logic syn thesis.
点击反馈