And finally, simulation results and verification by hardware test in FPGA show that the design of the IP core is valid and the proposed optimization strategy to reduce the memory is effective.
对以上优化设计方案进行了设计实现。仿真结果及FPGA硬件测试验证表明，文章提出的优化方案可行、有效，极大地降低了硬件资源占用和功耗。
The safety and rationality of dispatching plan is guaranteed by the safe verification and interactive simulation.
对调度计划进行校验和交互式模拟操作保证了操作的安全性和合理性。
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