The increased data bus width enables support for addressable memory space above the 4gb generally available on 32bit architectures.
增加的数据总线带宽实现了对32位架构上通常可用的4gb以上可寻址内存空间的支持。
A memory address consists of binary data being output on an appropriate bus which we call the address bus.
一个存储器地址是由输出到适宜的总线上的二进制数据所组成。这个总线我们称为地址总线。
The memory structure, constitution of data communication channel and system bus are analyzed, and the algorithm allocating, algorithm mapping and scheduling on the multiprocessor are discussed.
对系统的存储器结构、数据通信通道组成和系统总线结构进行了分析； 讨论了算法划分、算法的多处理器映射及调度；
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