a single clock cycle 单个时钟周期
This is the number of operations that must be completed in a single cycle of clock time.
这是在一个时钟周期内必须完成的操作数量。
Devadas has demonstrated that small circuits connected to the cores can calculate the allotment of bandwidth and switch the direction of the connections in a single clock cycle.
Devadas已经成功演示了一种能计算带宽分配且能在一个时钟周期内改变连接传输方向的小型电路。
In this thesis we discuss such a DSP, which USES a clustered VLIW architecture and can perform multiple operations simultaneously during a single clock cycle.
本文讨论这样一款DSP，它采用分簇的VLIW体系结构，能够在单个时钟周期同时执行多个操作。
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