Clock Tree Synthesis is important in the backend-end design of chip design, and the clock skew has become the major part of constraints that limit system clock frequency.

时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。

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Single frequency source is usually used as local oscillator in communication system and radar system, also as a reference clock in digital circuits, so it is a extensive-applied technique.

固定频率源可以在在通讯系统和雷达系统中作为本机振荡器，也可以作为数字电路的基准时钟信号，因此得到了广泛的应用。

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This paper introduces the method of clock calibration to VCXO in system, based on GPS and CPLD. It can solve the problem of frequency offset because of Crystal worse behavior in Long-term use.

本文还给出了基于GPS芯片和CPLD，对系统压控晶振时钟进行校准的实现方法，有效解决了由于长时间使用，晶振自身特性变化，造成的频率偏移现象。

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