... gate level logic simulation 门级逻辑模拟 gate-level logic simulation 门级逻辑模拟 hierarchical logic high level 分级逻辑高电平 ...
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gate level logic simulation [计] 门级逻辑模拟
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The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
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