This experimental quide to the digital logic comprises two parts: combinational logic and sequential logic.
本实验指导书分为两大部分：组合逻辑，时序逻辑。
The methods have useful reference value to using correctly flip-flops and designing sequential logic circuits.
这些方法对于正确使用触发器和设计时序逻辑电路有重要应用参考价值。
In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.
为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓冲器。
The race and hazard in the sequential logic circuit is quite essential and must be considered when designing logic circuit.
时序逻辑电路中的竞争冒险是电路设计中必须考虑到的重要方面。
It is demonstrated that the SRL can be used for both combinatorial and sequential logic functions, and as all-optical regeneration devices.
SRL不但可用来实现组合的和顺序的逻辑功能，还可用于全光再生器件。
The principle of using sequential logic circuit and 8031 monolithic computer for realizing continuous pulse duration measure are introduced.
主要介绍了用时序逻辑电路实现连续脉冲宽度测量的工作原理，并讨论了采用8031单片机的实现方案。
This paper presents a multiple fault test simulator for sequential logic circuit. The simulator is implemented in serial-parallel to save memory.
本文给出一个时序逻辑电路的多故障测试模拟程序。
The circuit includes a sequential logic drive circuit, a DC bias voltage circuit and a monolithic temperature control circuit for the focal plane array.
其中包括时序逻辑驱动电路、直流偏置电压电路及单芯片焦平面温度控制电路。
Building the transition relation of sequential logic circuit is one of the key technologies for applying model checking method to verify the sequential logic circuit.
有效地建立和表示时序逻辑电路的状态转移关系是应用模型检查方法验证时序逻辑电路的关键技术之一。
Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.
此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓冲器。
In this paper, DT flip - flop excitation table is developed, the design method of sequential logic circuits using DT flip - flop is presented, and the design example using the method is given.
导出了DT触发器的激励表，提出了应用DT触发器的时序逻辑电路的设计方法，并给出了设计实例。
Sequential logic synthesis is an important part of RTL synthesis system design.
时序逻辑综合是RTL综合系统设计中的一个重要部分。
Sequential logic synthesis is an important part of RTL synthesis system design.
时序逻辑综合是RTL综合系统设计中的一个重要部分。
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