Using clock as data has created various issues in timing closure, particularly in logic and physical synthesis.

使用时钟作为资料在定时关闭已经创造各式各样的问题，特别在逻辑和物理综合。

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The advantages of the method include better quality-of-result of a design, fewer timing closure iterations and less complex design flow.

该方法的优点包括更好的质量的结果的一个设计，更少的时序收敛的迭代和不太复杂的设计流程。

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A new method for layout design based on region constraints was presented to resolve the timing closure problem of physical design in deep sub-micron technology.

针对深亚微米工艺下版图设计中存在的时序收敛问题，提出了一种区域约束的版图设计方法。

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A new method for layout design based on region constraints was presented to resolve the timing closure problem of physical design in deep sub-micron technology.

针对深亚微米工艺下版图设计中存在的时序收敛问题，提出了一种区域约束的版图设计方法。

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